1. Field of the Invention
The present invention relates generally to data storage systems, and more particularly to timing jitter measurement.
2. Description of Related Art
In data storage systems, timing jitter is an important parameter for determining signal quality. Smaller timing jitter indicates better signal quality. Currently available technologies usually measure timing jitter with analog circuits and analyzers. FIG. 1A illustrates a currently available apparatus for measuring timing jitter. An incoming radio frequency (RF) signal may come from a media reader, e.g., a laser reader or a magnetic reader, and may be fed through an analog/digital converter (A/D) 101, an equalizer 102 and a limit equalizer 103. The digital signal at the output of the limit equalizer 103 is converted into an analog signal by a digital/analog converter (D/A) 105. An LPF (Low Pass Filter) 106 may receive the analog signal from the D/A 105, remove its high frequency parts and reconstruct it into a smoother analog signal. As shown in FIG. 1B, a slicer 107 may detect zero crossing (ZC) moments in the analog signal from the LPF 106. A PLL (Phase-Locked Loop) 104 may receive the analog signal from the limit equalizer 103 and provide a clock signal to the A/D 101, the equalizers 102 and 103, the D/A 105 and a TIA (Timing Interval Analyzer) 108. As shown in FIG. 1B, the TIA 108 may compare the detected zero crossing moments from the slicer 107, represented by solid lines, and expected zero crossing moments from the PLL 104, e.g., the falling edges t0, t1 . . . t4 of each clock pulse represented by dash lines, and output the time differences therebetween as the timing jitter.
Since the D/A 105 and the LPF 106 are used to transform the output of the limit equalizer 103 from the digital domain to the analog domain, and the slicer 107 is used to detect the zero crossing moments, the input signal of the TIA 108 does not have more information, useful for timing jitter calculation, than does the output signal of the limit equalizer 103. However, it can be difficult to integrate these analog devices into chips.
Therefore, it may be desirable to provide an all digital jitter measurement circuit.